Multi-channel control systems

ABSTRACT

A control system for controlling a number of different variables in accordance with input information has a plurality of separate control channels each including a digital store, preferably a shift register, for storing input and output data and also control parameters appropriate to that channel. The channels are connected sequentially to a common data processing unit which makes use of a common algorithm store. Selection of algorithms for the various channels is effected by a pin board matrix thereby providing a visual display of the selected algorithms. An operator&#39;s console has facilities for selecting any channel and displaying information from the channel store on monitors. A key-board enables the operator to change control parameters of the selected channel. Each channel also includes means for analogue-to-digital conversion of input information, digital to analogue conversion of output information and holding means for output analogue data.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation-in-part of co-pending applicationSer. No. 120,170 filed Mar. 2, 1971, now abandoned.

BACKGROUND OF THE INVENTION

This invention relates to controllers providing an electrical outputsignal in response to input signals.

Controllers are widely used for many purposes, for example in automaticprocess controls for manufacturing or chemical operations. Suchcontrollers are usually employed in conjunction with transducers whichsense the magnitudes of parameters relating to the operation to becontrolled and which provide electrical signals fed to the controller.The controller processes these signals and provides electrical outputsignals for control purposes. The present invention is concerned with acontroller having a number of information inputs and providing outputsfor effecting a number of control operations. In the controller of thepresent invention, processing is effected digitally on a time-sharedbasis. Apart from the time-shared operation of the digital processingequipment, the control operations may be independent in the sense thatinput information from one source may be processed and used to providean output signal independently of any other input information. It isthus convenient to refer to "control channels", a channel beingconcerned with taking input information for feeding to the processor andproviding a corresponding processed output signal. Reference may be madeto U.S. Pat. No. 3,374,464 and 3,267,434 as examples of priormulti-channel control system using digital data processing.

In prior types of multi-channel control systems using digital dataprocessing, the programming of the data processing part of the equipmenthas been a complex job requiring special training and experience. It isa principal object of the present invention to provide an improved formof multi-channel controller in which the setting up of the algorithmsfor processing the information for the various channels is simply andreadily done and in which the selected algorithms are visuallydisplayed.

Although on one channel incoming information may be processed to providean output, inter-connection of channels may be required for variouspurposes, e.g. input information may be used in more than one channel oroutput information from one channel may be used as an input in anotherchannel. As explained later such interconnection may be provided andvisually displayed in the controller of the present invention. It isconvenient however in the first place to consider the equipment ashaving a number of control channels which can be operated independentlyon a time-shared basis utilising commondata processing equipment.

SUMMARY OF THE INVENTION

According to the present invention, in a control system having a numberof control channels there is provided a common data processing unit forprocessing data in digital form, and a plurality of separate controlchannels, each channel having a digital store for storing inputinformation, output information and other data relevant to that channel,sequencing means for sequentially connecting the data processing unit tothe stores associated with the various channels, an algorithm store forproviding instructions to the data processing unit for appropriatelyprocessing the input data on the selected channel and feeding theprocessed input data to the output store of that channel, and a channelspecification store comprising a matrix having data storage, manualentry and visual display, means connecting said channel specificationstore to said processing unit to provide the processing unit withpredetermined information for the various channels, and sequencing meansscanning said matrix in step with the sequential scanning of the variouschannels.

The matrix in the channel specification store is conveniently apin-board matrix. This enables the selection of the required algorithmsto be effected manually and gives a visual display of the enteredinformation. This provides a simple convenient means by which theoperator can programme the system so as to give the required functions.By the use of the patch cords, it is possible to make interconnectionson the matrix, so as to feed information on one channel into anotherchannel.

Heretofore, in multi channel control systems, it has been the practiceeither to have a fixed program determining the operation of the systemmodifiable only by reprogramming or to make use of a teletypewriter forputting in program instructions. The fixed programs are usuallymodifiable by means of a paper tape or magnetic tape input and anychange in such a program usually requires the services of a computerprogrammer and cannot be effected by a control engineer in a processcontrol plant. The teletypewriter enables programs to be changed butrequires the use of relatively complex coding schemes which must belearned by the operator before any program change can be effected.

The arrangement of the present invention provides a simple system whichcan readily be used by a control engineer since the possible functionsare visually displayed and selection can be effected by insertion ofpins in appropriate sockets in the matrix.

Typically the system might be arranged to handle up to say a hundredchannels dealing with each periodically as required. It would be readilypossible to process the data in a hundred channels in less than 1 secondbut, as will be explained later, it is often desirable to process dataat longer time intervals than this in order that significant changes ininput information can be sensed and utilised to provide informationabout the rate of change. The sequencing means preferably therefore isadjustable or can be preset to connect the various channels to the dataprocessing unit at time intervals selected to be appropriate for theindividual channels.

Each channel is basically equivalent to a single loop controller. Foreach channel, the input signals may be analogue signals, typically acurrent input. A current input in any predetermined current range may beconverted by an appropriate terminating resistor so as to produce asignal in a standard voltage range e.g. 1 to 5 volts. The voltagesignals may be scanned by switches, for example field effect transistorswitches, controlled by the channel sequencing system and presented inturn to a high speed analogue-to-digital converter. The resultantdigital signal is then put into the input data store for the appropriatechannel. Alternatively each channel may have a separateanalogue-to-digital converter for feeding the input analogue informationinto the input data store in digital form.

The output store of a channel has information in digital form which maybe converted into analogue form e.g. a current output. Thisdigital-to-analogue conversion is conveniently effected by convertingthe digital signal to a pulse train and then smoothing the pulse trainwith an averaging circuit. The digital to pulse train conversion may beeffected as described in the specification of U.S. Pat. No. 3,605,026 ofK. R. R. Bowden filed 14th July 1969 and entitled "Apparatus forproviding a pulse train having a mean frequency proportional to adigital number". The conversion, as described in that specification, iseffected by cycling a number in a shift register in such a way as topresent each bit of the number, at the output of the shift register, fora proportion of the time in accordance with the significance of the bit.The instantaneous output of the shift register is then smoothed togenerate a D.C. voltage proportional to the number in the shift registerand this voltage in turn is converted into the required current outputsignal. The shift pulse train required for such a digital analogueconversion is complex but one pulse generator may be used to provide theshift trains for any number of such digital-to-analogue converters.

If a shift register is used for the digital-to-analogue conversion ofthe output of a channel, it is convenient to use a single shift registerfor each channel to store not only the output information but also theinput information and other data required during the processing for thatchannel. The shift pulse generator is then arranged so that only theoutput number stops at the end of the register; data transfers in andout of the register are done as the numbers go past in the course oftheir normal cycling, using synchronising information from the shiftpulse generator.

The digital data processing unit processes the input information usingalgorithms from the algorithm store as directed by a channelspecification store. The algorithm store preferably contains algorithmsto provide for all normal control facilities such as three-term controlwith cascade control of set point and feed forward, ratio control, and ageneral lead/lag/gain/limiting algorithm. The control data to be usedwith the algorithms, e.g. set-point values, integral and derivative timeconstants e.g., are preferably entered and stored in the stores for thevarious channels as described later.

Monitoring facilities may be provided for monitoring the input andoutput information in the input and output data stores. Manual controlfacilities may also be provided.

The monitoring facilities may include manually operable selector meansto select a channel and visual display means displaying the input andoutput information in the selected channel store. Preferably manuallyoperable means are provided for monitoring and inputting set-pointand/or other control information into the selected channel store. Forthis purpose a numerical keyboard information entry means may beprovided.

Additionally a digital interface may be provided via which other devicesmay be connected. For example a computer could be attached in asupervisory mode for adjusting set-points, time constants etc., or itcould take over direct control of some channels either permanently ortemporarily. A set-point sequencer may be provided to change any or allof the set-points or other constants according to a prearranged sequenceto assist with start-up or other rapidly changing conditions.

For each channel there may be provided a fixed store for providing fixedinformation. Physically these fixed stores may be located together; theymay be arranged for setting by the user. For example, the fixed storesfor all the channels may comprise a single diode pin-board matrixconstituting the aforementioned channel specification store. This matrixmay be scanned in step with the sequential scanning of the variouschannels. Such a pin-board matrix may have a row (or column) of socketsfor each channel. These are preferably arranged so that the requiredfunction (e.g. the required algorithm) for each channel is selected byputting pins in appropriately labelled sockets or by puttingappropriately labelled multi-contact pins in a socket. For example,there might be "proportional", "integral" and "derivative" sockets, pinsbeing put in all three if three-term control is required or in only oneor two if only one or two term control is required. Alternatively, asingle multi-contact (e.g. four contact) socket may be provided intowhich an appropriate pin is inserted according to the type of controlrequired. Similarly further sockets may be provided to select otherfunctions such as alarm operation or sampling interval. Patch cords maybe used on such a pin-board matrix for inter-channel connections. e.g.to define a connection from the output of one channel to the input ofanother.

Conveniently an intermediate register is employed associated with thedata processing unit, the complete information from the data storesassociated with each channel being transferred to the intermediateregister in sequence when the data from that channel is to be processed.The data processing unit can utilise this register and a small amount ofworking storage to perform the required processing; at the end of theprocessing, the required output together with other quantities to beremembered, such as the value of the integral term in a three-termcontrol channel are put into the appropriate positions in theintermediate register. At a last stage in dealing with a channel, thenew contents of the intermediate register are transferred to theappropriate channel data store.

Preferably "hold" facilities are provided on the output of each channel,for example by applying the output voltage to a capacitor connected inthe input of a voltage to current converter powered from a batterybacked-up power supply. Manual back-up raise/lower facilities may beprovided for manual change of the output. The operator's console mayhave a switch for switching all the channels onto the hold facility soas to isolate and maintain the output signal in case of equipmentfailure. Automatic means may be provided for operating this switch fromfault-detection circuits. Critical control loops may have individualanalogue backup controllers incorporated in the channel input/outputcircuits, brought into operation manually or automatically as required.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a basic block diagram of a controller embodying the invention;

FIG. 2 shows the controller of FIG. 1 in further detail;

FIG. 3 illustrates diagrammatically in operator's console for thecontroller of FIG. 1;

FIG. 4 is a diagram, for explanatory purposes, of a temperature controlloop with cascade operation;

FIG. 5 is a diagram showing part of a pin-board matrix used in thecontroller of FIG. 1 and illustrating how it is set-up to provide thecontrol loop of FIG. 4;

FIG. 6 is a logic circuit diagram showing the arrangement of thesampling interval counters and comparators;

FIG. 7 is a diagram showing typical waveforms in the circuit of FIG. 6;

FIG. 8 is a diagram showing the method of operation of an inter-channellink section of a channel function matrix;

FIG. 9 illustrates a modification of part of FIG. 2.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1 there is shown an arithmetic unit 10 with analgorithm store 11 and a channel selector 12 for effecting sequentialselection of the channels. As previously indicated, there may be a largenumber of channels, e.g. a hundred channels. Each provides inputinformation for processing and provides output control signals orpossible output signals for feeding to other channels. These channelsare indicated diagrammatically by the three pairs of leads 13, 14, 15each pair comprising an input and an output. The input and outputcircuits are represented by the block 16 which includesanalogue-to-digital converters for the input informationdigital-to-analogue converters for the output information and a datastore for each channel. This data store is typically a separate 100-bitshift register for each channel. This shift register may be used, aspreviously explained, for the digital-to-analogue conversion as well asfor storing input data, output data and data required for the particularchannel. An operator's console shown in FIG. 3 and to be described infurther detail later has monitoring and manual control facilitiesindicated in FIG. 1 diagrammatically at 19, these serving to displayinput data and output control data and also the set-point. Conveniently,the operator has a channel selector, e.g. push-buttons, so that he canselect any one channel and only information about that channel isdisplayed. The operator has facilities for altering set-points and otherinformation, including direct manual control of any output. Informationto be entered is set in by a keyboard and is displayed for checkingbefore being transferred into the control system. The operator also has"hold" facilities previously described. The construction and use ofoperator's consoles in control system is well known and reference may bemade, for example, to "Instrument Engineers' Handbook" edited by Bela G.Liptak, Chilton Book Co. Phila. 1970, Pages 1091-1095 for a descriptionof a typical console construction.

Referring now to FIG. 2, the controller is shown in more detail. Thearithmetic unit 10 is connected by a highway indicated by 20, 21 to thechannel data stores, or hybrid stores, of which three are showndiagrammatically at 22, 23 and 24. These stores each comprise a shiftregister for storing digital data. At any time, the particular hybridstore to be connected to the data highway 20, 21 is selected by thechannel number highway 92. The source of the channel number on thishighway 92 is normally the channel number counter 31, but, duringallocated intervals in each second, as hereinafter described the consoleand digital interface each have an opportunity to select a channel.

Each channel data store (alternatively referred to as a hybrid storebecause of its involvement in the digital-to-analogue conversion) mayhave an associated analogue-to-digital converter for converting inputinformation in analogue form into digital data to be put into the shiftregister as described later with reference to FIG. 9. In the arrangementillustrated in FIG. 2, however, there is a single analogue-to-digitalconverter as shown at 25. Analogue-to-digital converters are well knownand reference may be made to the aforementioned "Instrument Engineers'Handbook" pages 967-970 for a description of suitable high speedconverters. In the present embodiment with a single converter,sequential switching means are provided to switch the various analogueinputs to the converter and to switch the digital output from theconverter on to the data highway. This sequential switching iscontrolled by the channel number information on the channel numberhighway 92. At any one time, there can only be one number on thishighway and each hybrid store 22, 23 etc. contains switch means 96responsive to the appropriate channel number to connect the hybrid storeto the highway 20, 21 and converter 25. Input signals on the variouschannels are typically currents from remote transducers. Each inputcurrent is fed through a resistor to produce a voltage signal in apredetermined range, e.g. 1 to 5 volts. The voltage signals in thevarious channels are scanned sequentially under the control of thechannel number on lead 92 and the selected voltage is passed to theanalogue-to-digital converter 25 where it is smoothed with a suitabletime-constant to remove any high-frequency interference. Theanalogue-to-digital conversion conveniently utilises a ladder networkarrangement with switches controlled by flip-flops of a register so thatthe digital output number is built up bit-by-bit, with the mostsignificant bit first, by a series of trials and comparisons. Thereafterthe resultant number is shifted serially out of the register whenrequired. Each channel also includes means for converting output digitaldata into analogue form. For this purpose there is provided a shiftpulse generator 26 which generates shift pulses (as is described in theaforementioned U.S. Pat. No. 3,605,026 of Bowden filed July 14th 1969and entitled "Apparatus for Providing a Pulse Train having a meanfrequency proportional to a digital number") to bring each digit of thenumber to be converted into an output stage of the shift register forperiods of time corresponding to the significance of the bit. Theinstantaneous output voltage is then smoothed to generate a D.C. voltageproportional to the output information in the shift register and thisvoltage is in turn converted into the required current output signal.The digital-to-analogue conversion has a battery backed-up power supply27 and hold facilities 28 are provided on each output for automaticallyholding the output analogue voltage so that it is maintained in theevent of a failure of the main power supply or any part of thecontroller.

The arithmetic unit 10 may typically comprise a serial adder, anaccumulator register and two working registers. It is convenient howeveralso to have an intermediate register 17, data from a channel storerequired by the arithmetic unit being first transferred down the datahighway 20 to the intermediate register 17 in the arithmetic unit. Thearithmetic unit has access to any part of the intermediate register 17individually.

Before describing the equipment in detail, it is convenient to refer tothe principal components and to outline their function. Scanning of theinstruments in the program algorithm store is effected via control logic36 which feeds a program counter 37 and accepts information from twoprogram matrices 38, 39. Sequencing of the channels is controlled by aclock unit 40 which directly controls the aforementioned channel numbercounter 31. The output of the channel number counter 31 is fed into achannel number decoder 42 which drives the channel specification matrix43, 48, 49 and 112. The output from the sampling interval part 43 ofthis matrix is applied to a compartment 44 which is compared with theoutput from a sampling intervals counter 45. With a system having ahundred channels, the channel number counter might be stepped on by oneunit every 10 m secs. The sampling intervals counter 45 in this casewould be stepped on each second, i.e. after a complete sequence from thechannel number counter so as to give the appropriate control signals tothe control logic. The sampling interval matrix 43 has to provide, asdescribed below, outputs indicating in which of the scanning sequenceseach channel is to be sampled. Matrix 43 also feeds a scaler 47 in whichthis information together with information from a zero and span matrix48 is used to provide the appropriate displays for the operator'sconsole. The arithmetic unit 10 performs calculations in terms of 0 to100% of the input signal and therefore does not require information fromthe zero and span matrix.

The channel specification store 12 of FIG. 1 includes as shown in FIG.2, the sampling interval matrix 43, the zero and span matrix 48, and achannel function matrix 49 which is a diode plug-in pin-board to enablethe user to specify the nature of each channel and any interconnectionsbetween channels. This pin-board matrix, which will be described laterwith reference to FIG. 5, is not used to define a numerical constant forthe channel. It has however to indicate which of the algorithms providedis to be used for each channel and it therefore is employed directly togate out one or other of the algorithm stores 38, 39 to the arithmeticcontrol logic 36. It also defines in detail which parts of the chosenalgorithm are actually to be used. It may for example selectproportional plus integral control with feed forward from a generalisedthree-term control algorithm. The channel function matrix also definesinterchannel connections. This enables cascaded set-points and feedforward terms to be used as well as interconnections for inter-activecontrol. The pin-board 112 forming the matrix 49, as will be describedlater, has output sockets and input sockets; jumper wires are providedfor connecting output sockets and input sockets when an input for onechannel is to be taken from an output of another channel. The zero andspan matrix 48 is also driven from the channel number decoder 42 andprovides scaling information which is required for monitoring. Thechannel number decoder 42 also drives the sampling interval matrix 43which allows the user to specify the sampling interval for each channelaccording to its requirements. This sampling interval matrix may also bein the form of a diode plug-in board. This matrix 43 is providedbecause, as explained below, often it may be required not to deal withall the channels in sequence.

Turning now to a more detailed consideration, the channel scanningsystem is based on a 102 pps clock 40, which drives the channel numbercounter 31. This counter has 102 different states, each of whichpersists for about 10 ms, until a further clock pulse is received. 100of these states are real channel numbers, and are sent out inbinary-coded-decimal form on to an 8-wire parallel channel numberhighway 92, via a gate 93. During these intervals, the control action ofthe system is accomplished, as described later. While the channel numbercounter is in its 101st state, the operator-selected channel number fromthe console 19 is connected to the channel number highway 92 via a gate94, and a scaler 47 is activated, passing the required data between theconsole 19 and the operator-selected channel date store. While thechannel number counter 31 is in its 102nd state, a digital interface 46is allowed to specify a channel number via a gate 95, and to passinformation to and from the selected channel data store via the datahighway 20, 21. This digital interface is utilised for the attachment ofother digital equipment.

As well as selecting a particular channel data store for connection tothe data highway 20, 21 by conventional address decoding techniques, thechannel number highway 92 also feeds the channel number decoder 42.Decoders suitable for this purpose are widely used and are availablecommercially; as a typical example reference may be made to CambridgeThermionic Corporation decoders 780-2019 and 780-2024. This decoder 42duplicates the effect of the individual address-decoders associated withthe channel data (hybrid) stores 22, 23 and 24, decoding the 8-bitbinary coded-decimal channel number into 100 individual energizingsignals for the channel specification stores, which comprise thesampling interval matrix 43, the zero and span matrix 48, channelfunction matrix 49 and interchannel link section 112.

The channel specification stores 43, 48, 49 and 112 comprise pin-boardmatrices, that is to say, they have conventional X-Y conductor arrayswith facilities for making a connection, via a diode, between theX-conductor and the Y-conductor at any crossing point. Pin boardmatrices in themselves are well known and reference may be made to U.S.Pat. Nos. 3,027,534 and 3,145,329 for a description of such devices.Conveniently, the diode is mounted in a small plug or "pin" and thearray is constructed so that each crossing-point forms a socket intowhich a diode plug can be inserted. In the embodiment of the presentinvention being described, there are up to 100 X-conductors, eachenergized by the channel number decoder 42 when the channel numberhighway carries its corresponding channel number. The Y-conductors,which form the outputs of the stores, are therefore energized via anydiodes which are present along the particular X-conductor being drivenat the time. In this application, the presence of a diode pin in aparticular column (Y-conductor) in the channel function matrix 49 isused to indicate a requirement in the control function to be applied,for example that "proportional", or "integral" action is required (seelater description of the use of the matrix); in the zero and span matrix48 it is used to give details of the scaling requirements for aparticular channel's measured input signal, and in the sampling intervalmatrix 43, it is used to specify the required sampling interval forcontrol action in the channel.

Thus, when any channel has been selected by the presence of its address(channel number) on the channel number highway, the channel numberdecoder 42 and channel specification stores 43, 48 49 and 112 act tomake available on the store outputs all the necessary command signalsspecific to that particular channel, defining the function of thechannel in an overall sense. The manner in which the commands areimplemented differs in the three cases, and is described below.

Consider first the sampling interval matrix 43, whose purpose is tospecify how often the control action should occur for each channelseparately. The reason for this requirement is that the derivative timeconstant must not be more than a few times larger than the samplinginterval if the effects of noise on a measured input are not to besignificant, bearing in mind that the change in the input has to bemeasured each sampling interval. Thus, if the controlled process haslong time constants, it may be desirable to have relatively longsampling intervals, possibly of many minutes, for some channels. Theseven outputs of the matrix 43 for a selected channel are compared atcomparator 44 with signals derived from seven counters forming thesampling interval counters 45, and when total identity is found, thecomparator 44 gives an output signal to the control logic 36 instructingthat control action is required for the selected channel.

The logic and waveforms of the sampling interval counters and comparatorare shown in FIGS. 6 and 7, in which the input signals SIM 2 to SIM 11are the sampling interval matrix outputs. Referring to FIG. 6, an inputclock signal of a frequency 1 p.p.s. is applied on an input lead 100 toa first divider chain comprising divide-by-two stages 101, 102, 103, togive outputs Q₂ Q₄ Q₈ at 0.5, 0.25 and 0.125 pps. The clock signal isapplied to a second divider chain comprising divide-by-3 stages 104, 105to give outputs Q₃ and Q₉ of 1/3 and 1/9 p.p.s. Furthermore the clockoutput is applied to a divide by 5 unit 106 and a divide by 11 unit 107to give outputs Q₅ at 0.2 p.p.s. and Q11 at 1/11 p.p.s. By applyingcontrol inputs from the sampling interval matrix 43, as selected bydiode pins in the matrix pinboard, in the form of continuous voltagesignals on appropriate leads SIM2, SIM4, SIM8, SIM3, SIM9, SIM5, and SIM11 any single output Q₂ Q₄ Q₈ Q₉ Q₅ or Q₁₁ or any combination of theseoutputs is applied to an AND gate 108 making use of a simple logiccircuit comprising OR gates 109 and inverters 110. If two signals, e.g.Q₃ and Q₄ are fed to the AND gate 108, an output signal is thenproduced, and the sampling frequency, i.e. when coincidence of thesesignals occurs is 1/3 × 1/4 = 1/12 p.p.s. for the channel selected. Thisoutput indicates that control action is required for the selectedchannel every 12 seconds. The various waveforms are shown in FIG. 7. Anexample of output signal is shown in the bottom line of FIG. 7 for SIM 3and SIM 4 active, i.e. for a sampling interval of 3 × 4 = 12 seconds.For other sampling intervals, diode pins are inserted in matrix 43accordingly, such that when the column labels of the sampling intervalportion of the matrix pinboard (see FIG. 5) are multiplied together,they give the required intervals for each of the selected controlchannels. Note that, with the circuit shown in FIG. 6, only one pin canbe used in each of the groups of sockets, for any one channel. Note alsothat although the sampling interval counters 45 are only stepped on onceper second, the sampling interval matric 43 outputs change as thechannel scanning proceeds, so that the "control action required" signalproduced by comparator 44 (FIG. 6) is representative of each channel, asit is scanned. An advantage of this scheme is that a wide range ofsampling intervals is available, without the use of an individualcounter for each channel.

The zero and span matrix 48 of the channel specification stores hasY-conductor outputs which feed information (conveniently inbinary-coded-decimal form) to the scaler 47. The two quantitiesspecified by the coded matrix output are the zero (i.e. low end) andspan of the input signal range (typically 4 to 20 mA) in terms of theunits of the physical measurement involved. For example, a transducerproducing 4 to 20mA for temperatures of 300° to 500° C needs a zero of300 and a span of 200 specified, for correct scaling into engineeringunits for display on the console. The two numbers from matrix 48 areused in the scaler as a multiplying factor (the span) and an additionalterm (the zero) in converting the internal number range (0 to 1) intoengineering units for display. A conventional frequency-counting scaler,with dividers controlled by the required multiplying factors, can beimplemented in this scheme, and can be made reversible as is necessaryfor proper scaling of newly-entered values from the console to theinternal number range.

The scaling for display of both measured input and set-point for eachcontrol channel makes use of the same range factors. However, in scalingthe controller time-constants (integral and derivative) for display, thesampling interval is used instead, as a scale factor, since internally,the ratio of time constant to sampling interval is stored (in thechannel data stores 22, 23, 24) and used by the control algorithm. Thus,in FIG. 2, the outputs of the sampling interval matrix 43 also feed thescaler 47, and are allowed to control the scaling dividers whenappropriate.

The channel function matrix portion 49 of the channel specificationstores has Y-conductor outputs which feed the control logic 36 directly,to define the function of each channel in accordance with the selecteddiode positions on the matrix pinboard for each channel. To see howthese signals are used, the functioning of the control logic 36 must beconsidered, in relation to the program counter 37 and program stores 38,39, and the arithmetic unit 10. These five blocks form a simplecomputer, with numerical data input and output via the data highway 20,21 and with command inputs from the comparator 44 and the channelfunction matrix 49. For any particular channel, the appropriate fixedprogram selected from the program stores by the diode pin positions inthe pin matrix 49 is obeyed, step-by-step, in the conventional manner,and is completed in less than 10ms, so as to be ready for the scan toproceed to the next channel. Programs or algorithms appropriate to thevarious major functions to be provided for use by the controller arestored in the program stores, or matrices 38, 39, of which there mayconveniently be one program for each major function type, e.g. one for"PID" control, one for "Sum, Difference, Product, Ratio" functions, onefor "Lead-Lag" function, etc. Then, the presence of a channel functionmatrix output on the Y-conductors of matrix portion 49 of the channelspecification matrix (due to a diode pin in a particular "algorithmselection" area, see FIG. 5) can be used directly by a program selectionswitch 111 within control logic 36 to select the related program, oralgorithm, stored at the location indicated by the Y-conductor output ofmatrix 49. The outputs of program stores 38, 39 so selected (typically12 to 16 bits for a simple instruction code) are fed into the controllogic for use in processing the data input on the selected channel. Theprogram matrices 38, 39 can be any form of store, but are convenientlyof a "read-only" type, since the facility for program changing is notrequired. Typically, a diode matrix (wired, not pluggable) or anintegrated-circuit "read-only memory" may be used to provide the fixedalgorithms.

The selected program for the channel under consideration is obeyed,step-by-step, by the control logic/arithmetic unit combination. Thecontrol logic converts the bit pattern of the selected programinstruction into gate-controlling signals for the arithmetic unit, suchthat the numerical input data received on data highway 20 is processedappropriately. When each instruction is finished, the control logicsteps the program counter 37 on to the next instruction, which is thenobeyed in its turn. At the end of the program for the selected channel,the control logic waits for a "start again" signal on a lead 113 fromthe 102 pps clock 40, at which time the process is repeated for the nextchannel.

The output of comparator 44 and the individual outputs from the channelfunction matrix 49, are brought into the control logic and are eachaddressable by program instructions to control conditional jumps, thatis, jumps in the program, or to omit certain sections of a program, ifthe output signal is in a 0 condition. Thus, for example, if thecomparator output is 0 for a selected channel, the whole of the controlprogram is omitted (because it is not yet a sampling time for thechannel); on the other hand, if the comparator output is 1, the programcontinues, and various sections of the selected program are brought intouse, or omitted, depending on the presence or absence of pins in thechannel function matrix columns, so as to give the desired totalfunction for the channel.

FIG. 3 illustrates the operator's console. This console is ofconventional construction and has a set of keys 50 for enteringnumerical information, these keys being conveniently located on a desktop. The console includes means for converting the keyed numbers intobinary coded decimal digital form. The console has a display unit 51containing also further keys as well as numerical visual displays. Atthe top of the display unit are a series of visual displays comprisingchannel number display 52, measured input display 53, set-point display54, an output display 55 and an extra monitor display 56. The operatorcan select a channel for monitoring and for inputting of control data bykeying the number on the keys 50, operating a switch 57 to effectchannel selection. The display 52 enables the operator to check that thecorrect channel number was keyed. During the 101st state of counter 31,the operator selected channel number is fed via gate 94 to effectconnection between the console and the selected channel data store. Thedisplay 53 then shows the measured input for this channel and displays54 and 56 show the control data at present in the store of the selectedchannel. The extra monitor display 56 displays information such asintegral time constant, derivative time constant, proportional band,sampling interval etc., as selected by a key of keys 58. Control data ischanged by keying the required number on keys 50, checking that thecorrect number has been keyed from the monitor 61 and then transferringthe data using a transfer key 59 and one of three selector keys 60according to whether it is set-point information, output (for manualcontrol) or other constant already selected by keys 58. The transfer iseffected during the 101st state of connector 31 when the console isconnected to data highway 92. The console also has a set of three keys62 to select "automatic control", "manual control" or "hold". The manualcontrol key enables the operator to effect manual control of any channelwhilst the hold key causes the selected channel to have its output heldby the aforementioned hold circuit 28. Three further keys 63 provide fornormal operation, all manual or all hold, enabling the operator tocut-out the controller and to hold the outputs with manual override onall the channels as required. Indicators 64 provide for the indicationof certain controller fault alarms, e.g. power supply failures,arithmetic check failure, or data transfer failure. Alarm levels mayalso be set for the input and output signals; these may be set in usingthe keyboard 50 and extra monitor 56. These alarms are convenientlyindicator lamps (not shown) in a flow diagram representing the processunder control. Audible or other alarms may also be provided.

It will be seen that the operator's console provides for the inputtingof numerical data into the stores of the various channels are requiredfor control purposes. The way this information and the input datarelating to the process is utilised in the various control channelsdepends on the algorithm stores. The algorithms are selected using apin-board and are not controlled from the console; it will be understoodthat for any given process, it would not normally be necessary to changethe allocation of control algorithms once they have been selected. FIG.5 shoes part of a diode matric pin-board 70 forming the channel thechannel specification store. This pin-board has a series of rowscorresponding to the various channels and has channel identificationreferences and numbers in the two left hand columns 71, 72. In thealgorithm section corresponding to matrix portion 49, there are threecolumns marked P, I and D. If, in any row, a pin is inserted in columnP, a proportional term is introduced into the control loop for thatchannel. If a pin is inserted in the column I, an integral term isintroduced into the control loop and if a pin is inserted in the columnD, a derivative term is inserted in the control loop. The pin-boardmatrix selects only the algorithm to be applied to the control loop inthis respect, the numerical constants being stored in the data stores ofthe various channels. The algorithm section 49 of the pin-board 70 alsohas columns enabling sum, difference, product and ratio terms to be usedand also provides for lead-lag algorithms. The pin-board also has aninterchannel link section 112 (FIG. 2) for making interchannel linksusing patch cords as shown for example at 73 (FIG. 5) for connecting anoutput column socket for one channel to an input column socket foranother channel. The pin-board also has columns 74 for specifyingalarms, columns 75 in the interval matrix portion 43 for controllingsampling intervals and columns for other control functions. The columns75 constitute the inputs for signals SIM2 SIM4 etc. These signals areactivated by plugging diode pins in the appropriate sockets in columns75.

FIG. 8 illustrates the electrical circuit arrangement for effecting aninterchannel link on the pin-board to permit of the automatic linking ofthe input or output of a channel for further use in another channel,instead of the normal inputs to that channel. Referring to FIG. 8, atthe right hand side is shown an input matrix comprising X-conductors120, 4 conductors 121 and sockets 122. Interchannel linking is achievedby using a link (73 in FIG. 5) containing a transistor 124 in one plugand two diodes 125 in the other. The right-hand (transistor) end of thelink is energized by driving the transistor emitter low (by the channelnumber decoder, as for the rest of the matrix) and by driving theappropriate Y-conductor (and therefore the transistor base) high. Thisdrive to the Y-conductor is under program control, and thus can beactivated whenever the program is looking for a linked input. The twodiodes at the left-hand end of the link both conduct when the transistoris turned on in this manner, activating one input of each of the twoencoders 126 wired from the "source" sockets 127 as shown in FIG. 8.There are a pair of such sockets 127 for each channel so that, ifrequired, two links 173 may be used to obtain data from that channel forprocessing. The source sockets are connected to leads 129 in a mannercorresponding to the channel number. Thus the encoders 126 generatebinary-coded-decimal versions of their single-wire channel numberinputs, so the output of the encoders is a b.c.d. version of the channelnumber corresponding to the source end of the link. At such times, thechannel number highway 92, to the channel data stores only, is switchedby a switch 128 (FIG. 2) away from the channel number counter 31 and tothis encoded "link source channel number" from encoders 126. Thearithmetic unit can then collect data, via the data highway, from thatchannel's data store, as appropriate to the functions involved.

The use of the pin-board will be made clear by considering, as anexample, the temperature control loop shown in FIG. 4 in whichtemperature of a fluid flow along a flow path 80 in the directionindicated by the arrow 81 is to be controlled using a heater 82. Atemperature transmitter 83 provides a measured input to a first channel84 of the controller 85. This channel provides proportional plusintegral control with a setpoint defined by the operator and its outputis used to provide the set-point for a second channel controller 86.This second channel obtains its measured input from a temperaturetransmitter 87 and provides proportional plus derivative control givingan output which is applied to a current-to-power converter 88 feedingthe heater 82. FIG. 5 shows the setting up of the pin-board for thiscontrol. For the first channel, designated TC01 on the board, pins 90are inserted in the proportional and integral columns of the algorithmsection. For the second channel, designated TC02, pins 91 are insertedin the proportional and derivative columns. The link 73 connected to thesource socket 127 of the first channel results in the address of thefirst channel being encoded by encoders 126. The presence of such anumber operates switch 128 so that the number of the first channel isfed to the hybrid stores and thus the first channel data is fed to thearithmetic unit. The four input sockets 122 enable the operator toconnect the output of the first channel to the appropriate input of thesecond channel (in this case the set-point input). It will be seen thatthe setting up of the required algorithms does not require any computerprogramming knowledge and can readily be done as soon as the controlrequirements are defined. The individual control channels can provideone, two or three term control. Cascade and feed forward connections canbe effected and other algorithms can readily be provided.

As previously explained, the operator can set in set-point or othercontrol data as required. The digital interface 50 may be used forsetting a sequence of set-points from an external data source forprogrammed control or during start-up or shut-down of a process.

FIG. 9 illustrates a modification of the arrangement of part of FIG. 2in which instead of having a separate analogue to digital converter 25used by the various channels on a time sharing basis, each channelincorporates its own converter. In FIG. 9, there is shown a preferredform of combined digital store and analogue-to-digital converter,particularly suitable for this purpose, which is described in U.S. Pat.application Ser. No. 283088 filed Aug. 23, 1972 and entitled "Analogueto Digital Converter", now U.S. Pat. No. 3,810,151.

Referring to FIG. 9, an input analogue voltage from one channel isapplied on a lead 210 to an analogue comparator 211 which has a secondanalogue input on a lead 212. This second input is derived from adigital signal in a memory unit which, in the embodiment illustrated, isa shift register 214 with a recirculation loop 215 including anadder/subtractor 216. The digital signal in the shift register 214 isconverted to analogue form by units 217 and 218 and applied to thecomparator 211 via lead 212. In this particular embodiment theconversion is effected in two stages. The unit 217 makes use of thesuccessive signals from the shift register, by shifting them atappropriate time intervals according to their significance, to provide asignal having a mark-to-space ratio representing the digital signal.This output is a pulse train having a mean frequency proportional to thedigital number. The output from unit 217 is converted into an analoguevoltage in unit 218. In the unit 217, the shifting of the signals in theshift register is effected by shift unit 219 (corresponding to unit 26of FIG. 2) which steps the data in the shift register so that each digitremains on the last stage of the shift register 214 for a time durationcorresponding to the significance of that digit. This output digit iscombined in an AND gate 220 with regularly repetitive pulses from apulse generator 221 which also synchronise the shift unit 219. Adigital-to-pulse train converter, such as the converter 217, isdescribed in the specification of the aforementioned U.S. Pat. No.3,605,026. Other types of digital to pulse-frequency or digital tomark-space ratio converters are known and may be used. The pulsefrequency output from unit 217 is converted to an analogue signal inunit 218 by an averaging circuit. This averaging circuit is illustrateddiagrammatically as comprising a shunt capacitor 222 charged through aseries resistor 223, the charging voltage being switched by a switch 224controlled by the pulses from unit 217 so that the resistor 223 isconnected to a voltage source 226 and to earth for periods of timecorresponding to the mark to space ratio of the pulse train.

The output from the comparator 211 has a polarity depending on the senseof the difference of the two inputs on leads 210, 212. This output isfed to an inverting integrator 230 which is periodically reset by asignal on a lead 231. The integrator gives a sawtooth output of polaritydepending on the sense of the input signal, which output is applied toboth positive and negative trigger units 232, 233. Depending on theoutput polarity, one or other of these trigger units will be triggeredwhen the integrator output reaches the trigger reference level. Theoutputs of the trigger units are fed via an OR gate 234 to one input ofan AND gate 235. The second input to this AND gate 235 is a timingsignal on a lead 236 from the shift circuit for the shift register 214indicating when the least significant digit is being circulated throughthe adder/subtractor 216. The output from the AND gate 235 provides thereset pulse on lead 231 and is also applied on a lead 237 as an enablingpulse to the adder/subtractor 216 so that the latter adds or subtractsone unit according as to whether a signal is present or absent in theoutput from the positive trigger unit 232. Thus, in each recirculationcycle of the digital data in the shift register, if one of the triggerunits 232, 233, has been triggered, the number will be increased ordecreased by one. The digital number will remain unchanged if neithertrigger unit has been triggered. The digital number is thus changed at arate and in a sense which will depend on the magnitude and sense of thedifference signal from the comparator 211 so as to make the digitalnumber in the shift register correspond to the magnitude of the analogueinput on lead 210. The digital output, in this embodiment, is taken outin serial form on a lead 238 from the recirculation loop 215.

The analogue-to-digital converter of FIG. 9 thus far described is usedas part of the hybrid store such as hybrid store 22 of FIG. 2, thedigital output on lead 238 being applied to a switching unit 96comprising a channel number comparator 250 responsive to input channelnumber information in highway 92 and controlling a switch 251 to feedthe digital information out on lead 20. Digital information from lead 21may be fed into the same shift register 214 and converted to analogueform by a digital-to-analogue converter, the output of which is appliedto the hold circuit 28. This digital-to-analogue converter may besimilar to the units 217 and 218 but the shift unit 219, the pulsegenerator 221 and the reference voltage source 226 can be common for allthe digital-to-analogue converters in all the channels.

I claim:
 1. In a control system having a plurality of separate controlchannels and a common means for processing data from all said channelsin digital form, each channel having an input line for receiving inputanalog information, an output line for output analog control signals, adigital store for storing input and output information, and convertermeans connected between said digital store and said input and outputlines for converting analog and digital information to digital andanalog information, respectively; sequencing means for connecting eachof said control channels in sequence to said common data processingmeans, the data processing means including a multiplicity of controlfunctions for use in processing said input information, the improvementcomprising:a channel function specification pin-board matrix having rowsof input lines, columns of output lines, and socket means forinterconnecting individual rows and columns, each of said rows of inputscorresponding to one of said channels and each of said columnscorresponding to one of said control functions; pin means manuallyinsertable in selected ones of said sockets whereby said matrix isresponsive to the connection of each of said channels to said commondata processing means to cause the input data from the selected channelto be processed in accordance with the control function selected by saidpin means.
 2. A control system as claimed in claim 1 wherein thepin-board has, for each channel, sockets for selecting proportional,integral and derivative terms.
 3. A control system as claimed in claim 1wherein the pin-board has, for each channel, at least one output socketand at least one input socket and wherein patch-cords are provided fordefining a connection from an output socket on the pin-board of onechannel to an input socket of another channel.
 4. A control system asclaimed in claim 1 wherein there is provided battery-powered hold meansoperative, for each channel, to hold the analogue output information. 5.A control system as claimed in claim 1 wherein said channelspecification matrix includes a sampling interval matrix connected tosaid sequencing means to be controlled thereby, and wherein means areprovided controlled by the sampling interval matrix to determine thesampling interval for each channel.
 6. A control system as claimed inclaim 1 wherein said channel specification matrix includes a zero andspan matrix controlled by said sequencing means and wherein there isprovided a scaler controlled by the zero and span matrix operative toscale digital data from any selected channel for monitoring or forinputting control data.
 7. In a control system for controlling a numberof different variables in accordance with input information in differentchannels and having for each channel, an input line for input analogueinformation, an output line for output analogue control signals, adigital store for storing input and output digital data, an analogue todigital converter connected to said input line to connect inputinformation to digital form, means for putting said input information indigital form into said digital store, a digital-to-analogue converterconnected between said digital store and said output line for convertingstored digital information into output analogue control signals, andcommon data processing equipment, the improvement comprising:thecombination of an arithmetic unit, a channel sequencer providing channelnumber information for the various channels in sequence, a data highwaybetween said digital stores and said arithmetic unit, switch meansassociated with the digital stores in each channel operatinglyresponsive to channel number information from said channel sequencer andoperating when the appropriate channel member is received to connectthat digital store for two-way communication with the arithmetic unit, apin board channel function matrix connected to said sequencer to giveoutput specifying functions to be performed on receipt of each channelnumber in sequence, said outputs being determined by the setting ofplugs in said pin board and control logic and program store meansconnected to said channel function matrix to provide program control forsaid arithmetic unit, said control logic and program store beingconnected to said channel function matrix to be controlled in accordancewith the pin setting on said pin board matrix.
 8. In a control systemhaving a plurality of separate control channels and a common means forprocessing data from all said channels in digital form, sequencing meansfor selecting and connecting each of said control channels in sequenceto said common data processing means, the improvement comprising:aninput line for each channel for receiving input analog information; anoutput line for each channel for output analog control signals; adigital store for storing input and output digital data; an analog todigital converter connected to said input line to convert inputinformation to digital form; means for storing said input information indigital form in said digital store; a digital to analog converterconnected between said digital store and said output line for convertingstored digital information into output analog control signals; and dataprocessing equipment common to all of said channels for processing saidstored digital information, said data processing equipment including apin board channel function matrix having channel selecting rows, outputfunction specifying columns, socket means at the intersections of saidrows and columns, and pin means manually insertable in selected socketmeans to interconnect selected rows and columns to cause selectedfunctions to be performed on said stored digital information for eachchannel in sequence, whereby the output for each channel is specified inaccordance with the column location of said pin means said pin meansproviding a visual indication of the selected function.
 9. The controlsystem of claim 8 wherein said data processing equipment furtherincludes a pin board inter-channel linking matrix having channelselecting rows, channel input and output columns, linking matrix socketmeans at the intersections of said channel rows and columns, and patchcord pin means manually insertable in selected socket means tointerconnect the inputs and outputs of selected linking matrix channels,said patch cord means providing a visual indication of the selectedinterconnections.
 10. The control system of claim 9, wherein said dataprocessing equipment further includes a pin board sampling intervalmatrix having channel selecting rows, sampling interval columns,sampling interval socket means at the intersections of said channelselecting rows and sampling interval columns, and additional pin meansmanually insertable in selected sampling interval socket means tointerconnect each selected channel to a selected sampling intervalcolumn; andan interval timing circuit connected to each samplinginterval column, the selection of a channel by said sequencing meansactivating the interval timing circuit selected for that channel toproduce a control action output signal to regulate the time intervals atwhich said selected output functions are performed on said storeddigital information.
 11. A method for automatic, independent digitalcontrol of a plurality of different variables on a time-shared basis inaccordance with selected functions, comprising:receiving incorresponding independent input-output channels analogue input datarepresenting each of said variables; converting said input data todigital form and storing said digital data in the correspondinginput-output channel; storing a plurality of selectable controlfunctions for use in processing said stored data; manuallyinterconnecting each of said channels with at least one of said storedcontrol functions; automatically and sequentially selecting saidchannels; shifting the stored digital data from the selected channel tocommon data processing means for processing in accordance with thecontrol functions manually selected for the said selected channel;shifting the processed digital data back to the selected input-outputchannel; storing the processed digital data in its correspondinginput-output channel; and converting said stored processed digital datato analog form for use in controlling said variable.
 12. The method ofclaim 11, wherein the step of manually interconnecting said channelswith said stored control functions comprises connecting each channel toa corresponding row of a pin board control function matrix;connectingeach of said stored control functions to a corresponding column of saidpin board control function; mechanically interconnecting selected rowsand columns of said pin board matrix, whereby selected functions areactivated for processing the digital data in specified channels, themechanical interconnections providing a visual indication of theselected function.